1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device with a plurality of dielectric films and electrode films alternately stacked therein.
2. Background Art
Conventionally, semiconductor memory devices, such as flash memories, have been fabricated by two-dimensionally integrating memory cells on the surface of a silicon substrate. In this type of semiconductor memory device, increase in the packaging density of memory cells is required to reduce cost per bit and increase memory capacity. However, recently, such increase in the packaging density has been difficult in terms of cost and technology.
Methods of stacking memory cells for three-dimensional integration are known as techniques for breaking through the limit of packaging density. However, in the method of simply stacking and patterning layer by layer, increase in the number of stacked layers results in increasing the number of processes and increasing cost. In particular, increase in the number of lithography steps for patterning the transistor structure is a primary factor in increased cost. Thus, reduction in chip area per bit by layer stacking is not so effective in reducing cost per bit as downscaling in the chip surface, and is not suitable as a method for increasing memory capacity.
In view of this problem, the present inventors proposed a simultaneously patterned three-dimensional stacked memory (see, e.g., JP-A-2007-266143(Kokai)). In this technique, select transistors in which vertically extending silicon pillars serve as channels are formed on a silicon substrate, and electrode films and dielectric films are alternately stacked thereon to form a stacked body. Subsequently, through holes are simultaneously formed in this stacked body. A charge storage layer is formed on the side surface of the through hole, and silicon is newly buried inside the through hole so as to be connected to the silicon pillar of the select transistor. Thus, a memory transistor is formed at each intersection between the electrode film and the silicon pillar. Then, select transistors are further formed thereon.
In this simultaneously patterned three-dimensional stacked memory, information can be stored by controlling the potential of each electrode film and each silicon pillar to transfer charge between the silicon pillar and the charge storage layer. In this technique, through holes are formed by simultaneously patterning the stacked body. Hence, increase in the number of stacked electrode films does not result in increasing the number of lithography steps, and cost increase can be limited.
However, in such a simultaneously patterned three-dimensional stacked memory, reading data stored in the memory transistor requires passing a sense current through the silicon pillar. To ensure reliability in reading data, it is necessary to sufficiently decrease the resistance of the connecting portion between the body portion of the select transistor and the body portion of the memory transistor in the silicon pillar. However, this connecting portion includes a polysilicon-polysilicon contact interface, and it is extremely difficult to reduce its contact resistance.